Senior STA Timing Engineer

Join us as a Senior STA Timing Engineer, where you will develop and validate timing constraints for advanced chip designs. Take ownership of timing analysis at block, sub-chip, and full-chip levels, collaborating with cross-functional teams. Ideal for experienced engineers with expertise in SDC, STA, and scripting languages.

Skills: sdc validation, timing exception handling, primetime, perl, tcl, python, makefile, dft modes, synopsys fusion compiler, tessent dft insertion, cross-functional collaboration, problem solving, communication skills, static timing analysis, system on a chip (soc)