Splunk
ASIC Engineering Technical Leader (RTL Design/SOC | 8- 14 Years)
- Bangalore, India · On-site
- Salary not published
- Posted 4 weeks ago
From Splunk's careers page
Status: listed on the employer's own careers page when we last checked (daily). Confirm on their site before applying.
About the role
Join our team as an ASIC Engineering Technical Leader, driving the design and implementation of high-performance ASIC chips. Lead architectural and implementation efforts, ensuring best industry practices. Ideal for experienced ASIC engineers with strong RTL design expertise and a proven track record in high-volume product development.
Skills: asic design, rtl design, systemverilog, verilog, vcs, spyglass, cdc, formal verification, synthesis, system debugging, system bringup, system validation, power optimization, area optimization, timing analysis, flow automation, logic optimization, python, c, c++, perl, makefiles, lab validation, tape-out, specification, team leadership, interpersonal skills
What they ask for vs. your profile
Must have
- C++
- Leadership
- Python
- Team management