Splunk
ASIC Design Verification Engineer | UVM | Exp. 8+ years
- Bangalore, India · On-site
- Salary not published
- Posted 6 months ago
From Splunk's careers page
Status: listed on the employer's own careers page when we last checked (daily). Confirm on their site before applying.
About the role
Join our team as a ASIC Design Verification Engineer, where you will define, design, and verify ASIC and subsystems for Cisco platforms. You will architect and develop DV infrastructure, develop test plans, and ensure RTL quality. Ideal candidates have significant ASIC verification experience and expertise in UVM/System Verilog.
Skills: debugging, protocol knowledge, asic verification, ethernet, verification coverage, collaboration, emulation testing, gate level simulations, system verilog, uvm, problem solving, test benches
What they ask for vs. your profile
Must have
- Network administration
- Problem solving