Splunk
From Splunk's careers page
Status: listed on the employer's own careers page when we last checked (daily). Confirm on their site before applying.
You will architect and develop DV infrastructure, develop test plans, and ensure RTL quality.
We are recruiting a ASIC Design Verification Engineer to define, design, and verify ASIC and subsystems for Cisco platforms. You will architect and develop DV infrastructure, develop test plans, and ensure RTL quality. Ideal for candidates with significant ASIC verification experience and expertise in UVM/System Verilog.
Skills: asic design verification, uvm, system verilog, asic subsystem development, test bench development, perl, python, scripting, debugging, integration testing, code review, functional coverage, block architecture, cluster environment design, top-level verification, forwarding logic, p4, veloce, palladium, zebu, haps, formal verification, pcie, ethernet, rdma, tcp
A free account lets you apply, save this job, see how well you match and check your resume against it.
Scores your resume against this job the way resume scanners do: the job's hard and soft skills, searchability, recruiter tips and formatting.
Create a free account to see your score. Your resume stays in this browser until then, and we never store it.
Already a member? Sign in