About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description
The Role
As a Staff Physical Design Engineer, you will be responsible for developing and perfecting the RTL-to-GDS implementation flow for our high-performance CPU cores. You will take ownership of advanced implementation recipes, driving PPA (Power, Performance, Area) closure on leading-edge N3/N2 process nodes. This role combines deep technical execution with the development of automated, ML-enhanced methodologies to ensure our CPU designs hit aggressive frequency and power targets.
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Key Responsibilities
Flow Development & Execution: Develop, validate, and deploy production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler
PPA Optimization: Drive block-level and hierarchical PPA closure, utilizing advanced techniques in timing-driven placement, CTS, and routing.
ML Implementation: Hands-on deployment of ML optimization tools (DSO.ai) to automate design space exploration and achieve optimal PPA results.
Technical Support: Serve as the first line of defense for flow and tool-related issues, working closely with the methodology team to resolve bottlenecks.
Collaboration: Partner with IP teams (SRAM/Std Cell) to characterize and model PPA impacts on the overall flow.
Automation: Create and maintain robust Tcl/Python scripts to improve flow efficiency and ensure repeatable, predictable results across design iterations.
Requirements
Experience: 7+ years of experience in Physical Design/Methodology, with a focus on high-performance digital implementation.
Node Knowledge: Proven experience with FinFET nodes (N5/N3); understanding of N2/GAAFET challenges is a plus.
Tool Proficiency: Expert knowledge of the Synopsys digital implementation suite (Fusion Compiler, ICC2, PrimeTime, StarRC).
Hierarchical Design: Strong understanding of hierarchical physical design, including floorplanning, pin assignment, and timing budgeting.
Automation Skills: High proficiency in Tcl and Python for flow customization and data analysis.
Problem Solving: A track record of solving complex timing and congestion issues in high-speed, high-density CPU blocks.
Additional Information
- This position requires a successful background and reference checks and satisfactory proof of your right to work in:
- India
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
