Experience in developing test bench from scratch -- UVM components : BFM, agents, monitor, scoreboard, checkers et al and 3rd party VIP integration.
Proficient in coding Pre-Silicon functional verifications tests to verify design to meet spec. requirements.
Creates efficient test plans for RTL validation and Gate level simulations.
Expertise in System Verilog, UVM, and/or OVM based verification methodologies.
Experience in OOPs concepts, coverage driven constrained random validation.
Must have very good knowledge on AMBA standards (AXI, AHB, APB).
Looking for individual with Hands-on experience in Memory protocols such as - HBM2/HBM3 OR LPDDR4~5x OR GDDRx is highly desirable.
Any experience on high-speed protocols like - PCIe, Ethernet, High speed SerDes is a plus
Working knowledge of scripting, SVA.
Execution of DV test plan which includes
Creation/modification of the test bench.
Implementation of software/programming sequence.
Creation/integration of checkers and scoreboards from unit level UVM environment.
Resolution of compile and simulation errors.
Innovative optimizations to reduce simulation time.
Complex failure debug: Isolating design related failure by systematically identifying and eliminating issues related to
Test bench/programming sequence in close collaboration with unit verification engineers, logic designers and architects
Coverage sign-off - Code (block, expression, fsm), toggle and functional coverage
Continuous regressions (X-prop, Power-aware and performance runs ) and failure closure
Skills and Qualifications
Experience – 4 to 7 years
Qualifications
B.Tech/B.E/M.Tech/M.E
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