Interfacing with cross-functional teams like Verification, Validation. SoC and FW .
Ensuring quality of design using Lint and CDC checks.
Synthesis, Area and power optimization.
Developing the timing constraints ( SDC) and ECO scripts.
Necessary Skills / Attributes
.• Project Management. Working experience in complex IP Design to meet market leading PPA metrics
Experience in designing and RTL coding using Verilog /System Verilog/VHDL.
Design QC using lint/CDC/DFT
Compile , elaboration and simulations for QC. Experience with VCS/NCsim, Verdi, and Spyglass.
Understanding of storage controller Architectures, Peripherals, Buses/Interconnects and Power Management.
Understanding of Bus Architectures (AXI/AHB), NOC (Network-on-Chip ) and ARM CPU Architectures.
Experience in writing functional design doc and/or functional specifications.
Experience in synthesis using Synopsys Design Compiler ( DC) and developing timing constraints ( SDC) and Timing analysis.
Experience in developing/understanding of ECOs
Working experience in teams with collaboration of effort between Verification, SoC integration, Physical Design and DFT Additional Qualifications (preferred)
Experience in RTL integration tools like Magillem is added advantage.
Working experience in High speed serial protocols like PCIe, NVMe, UFS Familiarity with FPGA based development is additional plus
Team player, can-do attitude is desirable. Passion for working on cutting edge technologies and ability to debug is highly desirable.
Experience – 14 to 20 Years
Qualifications
B.Tech/B.E/M.Tech/M.E
Disclaimer
Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.
Skills and Qualifications
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