Rivian
From Rivian's careers page
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As a company, we constantly challenge what’s possible, never simply accepting what has always been done.
About Rivian Rivian is on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract. As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations. Role Summary As a DFT Engineer you will be responsible for defining, implementing and deploying advanced Design-for-Test (DFT) methodologies including Scan, MBIST, JTAG/iJTAG, mixed-signal IO tests. You will work with Front-end RTL Teams, Physical design team and Productization team. In this role you will own DFT insertion, verification, DRC check, and test coverage closure from RTL/netlist through post-silicon debug. Responsibilities Lead implementation of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, logic BIST, Functional Safety(FuSa) and Analog IP Tests. Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, Cell- aware, path delay fault models, diagnosis, and hierarchical test flows. Run and debug non-timing and SDF annotated gate level simulations Analyze test results and drive test coverage improvement and closure Develop ,validate and timing closure of DFT timing constraints for scan, BIST, and test modes Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up, debug and Silicon characterization Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing Exposure to Chiplet-based architectures, including Die-to-Die (D2D) test methodologies (e.g., UCIe interfaces) and Known Good Die (KGD) strategies. Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent experience. 5+ years of experience in DFT architecture, implementation, and verification for SoCs. Experience in DFT flow, including architecture, IP integration (e.g., Scan controllers, TAP, MBIST), and interaction with synthesis and verification flows. Experience with industry-leading EDA tools for DFT, such as Synopsys ( Fusion Compiler, TestMax) or Siemens EDA (Tessent, TestKompress). Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification DFT SDC Creations and Test mode Static Timing Analysis & Debug Experience working with Gate level simulation with timing & no-timing, debugging. Experience in ATE debug, or validation of DFT features. Pay Disclosure The listed base salary range for this role is $146,00 - $232,000 for San Francisco Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs. We offer a comprehensive package of benefits for full-time and part-time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short-term disability insurance, and long-term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian’s 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full-time employee coverage is effective on their first day of employment. Part-time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com. Equal Opportunity Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law. Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at candidateaccommodations@rivian.com. Candidate Data Privacy and Technology Rivian may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes (“Candidate Personal Data”). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian’s service providers, including providers of background checks, staffing services, and cloud services. Rivian may transfer or store internationally your Candidate Personal Data, including to or in the United States, Canada, the United Kingdom, and the European Union and in the cloud, and this data may be subject to the laws and accessible to the courts, law enforcement and national security authorities of such jurisdictions. How We Use AI in Our Hiring Process: To ensure transparency, we want candidates to know that Rivian uses iCIMS Talent Cloud Artificial Intelligence (TCAI) and AI-enabled tools to assist with screening, reviewing, organizing and highlighting profiles and applications that match the key requirements for each role. AI does not make hiring decisions: Qualified candidate applications are reviewed by a member of our team, and all decisions throughout the process are made by humans. We use AI to support efficiency and consistency, not to replace human judgment. We are committed to a fair, thoughtful, and equitable experience for every candidate. Participation in AI profile matching is entirely voluntary. If you prefer that your profile not be used in this process, you can opt out at any time. Opting out means your profile will be excluded from automated matching and will not be surfaced for additional roles through this system. Your current application remains active and will not be affected in any way. Interview Integrity & AI Policy Our interview process is designed to evaluate your personal technical foundation, real-time problem-solving logic, and structured capabilities. Therefore, the use of assistive generative AI tools to formulate or deliver your solutions during live interview sessions is not permitted. We care most about how you think — how you make sense of unclear requirements, weigh trade-offs, and explain why you chose one approach over another. We value your unique human perspective, your authenticity, and the journey it takes to reach a solution. Please note that we are currently not accepting applications from third party application services. Lead implementation of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, logic BIST, Functional Safety(FuSa) and Analog IP Tests. Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, Cell- aware, path delay fault models, diagnosis, and hierarchical test flows. Run and debug non-timing and SDF annotated gate level simulations Analyze test results and drive test coverage improvement and closure Develop ,validate and timing closure of DFT timing constraints for scan, BIST, and test modes Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up, debug and Silicon characterization Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing Exposure to Chiplet-based architectures, including Die-to-Die (D2D) test methodologies (e.g., UCIe interfaces) and Known Good Die (KGD) strategies. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent experience. 5+ years of experience in DFT architecture, implementation, and verification for SoCs. Experience in DFT flow, including architecture, IP integration (e.g., Scan controllers, TAP, MBIST), and interaction with synthesis and verification flows. Experience with industry-leading EDA tools for DFT, such as Synopsys ( Fusion Compiler, TestMax) or Siemens EDA (Tessent, TestKompress). Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification DFT SDC Creations and Test mode Static Timing Analysis & Debug Experience working with Gate level simulation with timing & no-timing, debugging. Experience in ATE debug, or validation of DFT features.
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