Riverlane
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About the role Delivering practical quantum error correction requires tightly integrated quantum and classical systems.
Internship 2027: Engineering - Boston
Boston, US | Full-time | Fixed-term| Hybrid
Salary: $35-$42 per hour, DOE
Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in materials and climate science to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent, and passion.
Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.
Delivering practical quantum error correction requires tightly integrated quantum and classical systems. Decoding algorithms must process large volumes of error data within demanding latency, bandwidth, compute and power constraints.
As an engineering Intern, you will investigate the classical computing architectures needed to support scalable, fault-tolerant quantum computers. Your project will sit at the intersection of quantum error correction, computer architecture and hardware-software co-design.
Depending on the project, you could explore efficient QEC decoding or predecoding methods, model the classical resources required by fault-tolerant quantum programs, or investigate how decoding workloads can be distributed across different levels of a computing system.
You will work alongside Riverlane’s researchers and engineers in Cambridge, Massachusetts, with support from a dedicated supervisor. Your work will contribute to our understanding of how QEC systems can meet the performance requirements of increasingly large quantum computers.
Contribute to a research project focused on the classical systems and architectures required for scalable quantum error correction
Investigate methods for reducing the compute, communication, memory, latency or power requirements associated with QEC
Develop algorithms, simulations or architectural models to evaluate potential approaches
Explore trade-offs between decoding performance, logical error suppression and classical resource requirements
Consider how QEC workloads could be implemented across software, FPGA, ASIC or other computing architectures
Collaborate with researchers and engineers working across QEC theory, decoding, software and hardware
Analyse results and communicate your findings through technical discussions, presentations and written reports
Produce clear, reproducible research code and supporting documentation
You must be a current student at the time of application, studying towards a Bachelor’s degree (second year or later), Master’s degree.
Quantum error correction or fault-tolerant quantum computing
Computer architecture or quantum-classical systems
Decoding algorithms or error-correcting codes
FPGA, ASIC or digital hardware design
Experience developing computational models, simulations or research software
Proficiency in Python, C, C++ or another relevant programming language
A strong understanding of computer systems and architecture
Excellent analytical and problem-solving skills
The ability to communicate complex technical ideas clearly
The ability to take initiative and work effectively with researchers and engineers from different disciplines
Authorisation to work in the United States for the duration of the internship
Even better if…
You have experience researching quantum LDPC or surface codes
You are familiar with QEC decoding or predecoding techniques
You have explored the classical resource requirements of fault-tolerant quantum computing
You have experience with hardware-software or compiler-hardware co-design
You have worked with RTL, SystemVerilog, FPGA or ASIC development workflows
You understand the latency, bandwidth or power constraints affecting quantum control and decoding systems
You have experience with scientific computing, quantum circuit simulation or QEC simulation tools
You have contributed to academic publications, open-source software or collaborative research projects
Important notes
You must be legally authorized to work in the United States for the duration of the internship
If you intend to work under Curricular Practical Training (CPT), Optional Practical Training (OPT) or another form of student employment authorization, you are responsible for obtaining the necessary approval before your start date
Any offer of employment will be contingent upon verification of your identity and authorization to work in the United States, as required by law
You must be available to work full-time for 10 to 12 weeks
You will be required to sign an agreement assigning ownership of intellectual property produced during your internship to Riverlane
This internship is based at our US office in Cambridge, Massachusetts
How to apply
Please upload your CV and a cover letter.
Your CV should include details of your education, research experience and relevant technical skills. Your cover letter should explain why you are applying for the internship and the skills and experience you would bring to the role.
Deadline
Please submit your application by November 6th, 2026
We will reimburse reasonable expenses incurred as part of your role, such as approved travel to meetings or conferences. We are unable to cover the cost of travelling to Cambridge, Massachusetts at the beginning or end of the internship or accommodation during the internship.
You can expect a diverse and collaborative working environment that brings together experts in software and hardware development, quantum information theory, physics, mathematics and other technical fields. Our global team represents more than 20 nationalities.
We also provide free snacks and refreshments and organize regular social and cultural events.
If you have any questions, please contact jobs@riverlane.com.
Riverlane is an equal opportunity employer. We welcome qualified applicants and consider them for employment without regard to race, color, religion, creed, sex, pregnancy, sexual orientation, gender identity or expression, national origin, ancestry, age, disability, genetic information, marital status, military or veteran status, or any other characteristic protected by applicable federal, state or local law.
We know that strong candidates may not meet every requirement listed. If you are interested in the opportunity and believe your experience could be relevant, we encourage you to apply.
Riverlane provides reasonable accommodations to applicants with disabilities. If you require an accommodation during the application or interview process, please let us know. We will be happy to help.
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