Identify gate-error bottlenecks (e.g., coherent control error, decoherence, leakage, crosstalk, TLS interactions) for single-pair as well as large-scale systems and isolate their physical origin through targeted experiments, benchmarking, and simulation.
Develop and harden calibration methods using techniques such as optimal pulse shaping, dynamical decoupling, and other error suppression strategies, with an emphasis on robustness and automation at scale.
Develop and improve metrology for full-processor Hamiltonian and characteristic extraction and correlate with gate performance. Turn that knowledge into actionable feedback for device design, fabrication, and control hardware teams, and drive those changes to closure.
Prepare novel Rigetti devices for use by internal applications development teams and external deployment.
Stay current with the literature and convert state-of-the-art techniques into working capability on production hardware.
- Contribute to the field of superconducting quantum computing by converting relevant findings into high-quality publications.
- Required Qualifications
- PhD in Physics, Applied Physics, Electrical Engineering, or a related field.
Significant hands-on experience calibrating and characterizing two-qubit gates on superconducting quantum devices; direct experience with tunable couplers is a strong plus.
Deep understanding of gate design, pulse engineering, and decoherence mechanisms, with a track record of connecting error diagnostics to concrete fidelity improvements.
Demonstrated ability to independently execute complex experimental efforts from concept to validated result.
Strong Python skills in a scientific context, and comfort building tools that others rely on.
Dogged experimental determination, with the judgment to balance depth of investigation against speed of iteration.
- Excellent communication skills and a team-first mindset in a strongly collaborative environment.
- Nice to Have
- Experience with quantum simulation frameworks such as QuTiP for gate and noise modeling.
Experience deploying calibration or benchmarking procedures across large multi-qubit processors in an industrial or startup setting.
Familiarity with randomized benchmarking variants, gate set tomography, cycle benchmarking, or other scalable error diagnostics.
Publication record or demonstrated results in high-fidelity entangling gates, error suppression, or quantum control.
Experience mentoring junior scientists or leading small technical teams.
