Rambus
From Rambus's careers page
Status: listed on the employer's own careers page when we last checked (daily). Confirm on their site before applying.
Overview As a Senior Principal Verification Engineer, the candidate will be reporting to the Director of Verification in this Full-Time position.
Overview
As a Senior Principal Verification Engineer, the candidate will be reporting to the Director of Verification in this Full-Time position. Successful applicants will have a highly visible role in product development and take ownership of defining and executing verification plans for exciting DDR memory interface products.
Create digital verification plans using datasheets, inputs from engineers/customers, and working closely with system and design engineers.
Implement digital test-benches in SystemVerilog and UVM to apply constrained random stimulus.
Implement UVM reference models to check digital DUT behavior.
Debug issues, Track bugs, functional coverage, and RTL code coverage
Work in a dynamic and interdisciplinary R&D group contributing to flow and methodology development
Mentor junior engineers
MS EE and 10+ years or PhD EE and 7+ years’ experience of Verification
Significant Experience with coding in System Verilog or Verilog and UVM methodology
Experience working in Analog/Mixed-signal products(DDR,HSS,PCIE etc.) is highly desirable
Significant Experience with standard ASIC Verification flow/software tools
Strong knowledge of scripting, Linux/Unix environment
Experience in leading and driving technical solutions across organization
The position requires good English written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
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