Support LEC, extraction correlation, QoR reporting and signoff review readiness
Collaborate with RTL, synthesis, PnR, DFT and methodology teams to resolve root causes
Required Skills & Expertise
5-10 years of relevant STA/timing closure experience at subsystem or full-chip level
Strong hands-on expertise in PrimeTime and/or Tempus
Strong SDC knowledge and experience debugging incorrect, incomplete or conflicting constraints
Experience with MCMM timing analysis, path-based debugging and timing ECO generation
Understanding of parasitic extraction using StarRC or equivalent
Working knowledge of LEC using Formality or equivalent
Exposure to implementation tools such as Innovus, ICC2 or Fusion Compiler for timing correlation
Ability to communicate timing risks and closure actions clearly to implementation and design teams
Preferred Skills
TCL scripting capability; Python is an advantage
Familiarity with hierarchical timing models and interface closure
Exposure to advanced-node timing effects without requiring proprietary programme details
Recruiter Knockout Questions
1. Has the candidate owned STA closure at subsystem or full-chip level, not only generated timing reports?
2. Can the candidate explain how they validate SDC constraints and identify unconstrained or incorrectly constrained paths?
3. Have they debugged MCMM setup/hold issues and driven implementable ECO actions?
4. Which PrimeTime/Tempus analyses were used hands-on, including SI and variation methodology where applicable?
5. Have they worked with PnR and RTL teams until timing signoff convergence?
Education
BE/BTech/MTech in Electronics, Electrical Engineering or a related discipline.
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