Ensure best practices in coverage-driven and assertion-based verification.
Execution
Oversee end-to-end DV tasks: design analysis, verification planning, testbench development, simulation, and coverage closure.
Drive adoption of advanced DV methodologies (formal, simulation, emulation) for efficiency and quality.
Review and optimize test plans, environments, and scripts for scalability and reuse.
Collaboration
Work closely with global design, architecture, and cross-functional teams to meet project milestones.
Communicate effectively with stakeholders on progress, risks, and mitigation plans.
Mentorship
Coach and mentor junior engineers, fostering technical growth and best practices.
Required Skills & Experience
Vast experience in IP-level design verification
Strong expertise in SystemVerilog/UVM and coverage-driven verification methodologies.
Proven experience architecting and maintaining complex SV/UVM environments.
Proficiency in constraint-random testing and achieving coverage closure.
Strong debugging skills using tools like Verdi or similar.
Exposure to wireless IPs (Wi-Fi, Modem PHY, DSP blocks) is a plus.
Familiarity with formal/static verification techniques.
Power-aware verification and Gate-Level Simulation (GLS) experience is highly desirable.
Scripting skills (Python, Perl) for automation.
Qualifications
Education: Bachelor’s or Master’s or PhD in Electrical/Electronics/Computer Science from a reputed institution.
Experience: 12-18 years
Soft Skills
Excellent communication and collaboration skills.
Ability to lead and motivate a technical team.
Strong problem-solving and decision-making abilities.
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