Understand the IP architecture, work with IP validation teams and Systems validation Lead/system content engineer to understand the validation requirements, develop/port/enhance the validation software content and bring up.
Own SoC frequent regression and execute end-to-end regression suite by considering SoC design corner cases wrt power and performance.
Executing SOC validation releases on bench in lab and supporting the SLT teams in Debug and enabling different features in the framework.
Use silicon debug hooks to measure power/performance/coverage and other KPI metrics
Work with a relevant team member for regular reporting of issues and failure of debugs.
Mandatory Skills
Basics of processor architecture, Multicore/Multiprocessor with SMP/MTE/heterogenous cores.
C language expertise for low level programming, Assembly language for any processor, C-assembly interworking
Operating systems/RTOS/Linux kernel internals, scheduling policies, locking mechanism, MMU/paging etc
Exposure to working on emulation/pre-si environment is added advantage
Using JTAG based debuggers, compilers/linkers
Should have good exposure to software development life cycle
Desired Skills
Exposure to SoC architecture paradigms – interconnects, power management, system level content validation
Software development for silicon enablement, silicon validation
Bring-up of hardware-software solution on FPGA/emulation platforms and on fresh SOC designs
Good knowledge of ARM Cortex-A7/A8) / x86 / PowerPC CPU and memory system architecture
Weakly ordered memory model/pipelining of memory systems/memory barriers
Software development towards higher performance of multi-threaded applications using lower power
Top level of ASIC design methodology is an added skill
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