Minimum Qualifications
8-12 years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or a Master's degree.
Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and common low‑power design patterns at the RTL level.
Familiarity with RTL power analysis and optimization using tools such as PowerArtist, PTPX, PowerPro or equivalent.
Familiarity with low-power design techniques, including clock gating, power gating, and managing dynamic vs. leakage power tradeoffs.
Knowledge of Emulation Power flow and methodology.
Knowledge of backend flows such as logic synthesis and place‑and‑route, and how RTL decisions impact post‑layout power and timing.
Hands-on experience of debugging RTL or gate‑level power anomalies and identifying root‑cause structures or scenarios.
Strong Python programming skills for building automation scripts, data pipelines, and AI/ML‑driven analysis flows for RTL power optimization.
Excellent debugging, analytical, and problem-solving skills using data-driven approach.
Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
Excellent collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.
Preferred Qualifications *
Knowledge of Graphics architecture
Knowledge of OpenGL and(or) Vulkan API libraries
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