Our team does Pre-Si validation for DDRSS IP across all the product tiers at Qualcomm. Our team is spread across Bangalore and Hyderabad site. As of now, we are looking to hire experienced hardware engineers and managers with solid technical talent and extremely good people management skills for our Bangalore team. We encourage people to gain thorough knowledge depth and breadth to enable novel test-bench / DV environment development, out of the box thinking to break the design in an unorthodox way. This would also encompass exploring and developing new technologies to make this process more robust.
The role generally entails a mixture of
Expertise of DDRSS DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
Planning & execution of feature additions and mode re-enablement on particular variants
Debug of regression signatures and identifying bug fixes
Developing/Deploying new tools for validation (Certitude, VC Formal, Fishtail)
Working with all stakeholders to ensure program success
Designation : Staff Engineer
No. of years experience - 8+
Minimum Qualifications
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.
Following skill set is required
Thorough understanding of Digital design concepts
Strong Debug, UVM, System Verilog
Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite
Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization
Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5)
Quick understanding of Specs and Standards and developing relevant and thorough test plans
Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening
Post-Si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage
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