Key Responsibilities
Develop Verification Plans: Understand design specifications and define the verification scope. Develop detailed test plans and verification infrastructure.
Execute Verification Tests: Implement and Execute verification test cases and debug complex issues. Implement and analyze System Verilog assertions and coverage (code, toggle, functional).
Collaborate with Teams: Work closely with architects, designers, and pre and post-silicon verification teams to accomplish tasks.
Innovate Solutions: Develop innovative solutions to verification challenges with minimal guidance. Ramp-up on new verification tools and methodologies. Explore innovative DV methodologies to continuously push the quality and efficiency of test benches.
Adhere to Standards: Maintain quality standards and best practices in test and verification processes.
Successful candidates will be required to collaborate with worldwide design, verification, silicon, and architecture teams to achieve all project goals. Hence, we are looking for candidates with strong communication skills.
Qualifications
Bachelor’s degree in Science, Engineering, or related field
Minimum 10+ years of design verification experience. *Senior positions to be offered to candidates with proven expertise in the relevant field
Good understanding of SystemVerilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
Experience in handling verification from Test planning to Tapeout for large-size HW Design
Preferred Qualifications
Master’s degree in Science, Engineering, or related field
15+ years industry experience with below skillset
Knowledge of SOC architecture, CPU architecture (ARM knowledge is helpful), DSP, AMBA Bus, DDR, GPU, Multimedia etc.
Exposure to ARM SBSA (Server Base System Architecture)
Experience with heterogenous multi-die system verification
Experience with D2D interfaces (e.g., UCIe, CXL) verification
Experience with pre-silicon emulation platform-based verification
Knowledge of Power design, architecture, and verification requirements
Displays a passion for debugging and strong problem-solving abilities
Experience with scripting languages such as Perl, Python is a plus
Assertion coding and converging on Formal tools, is a plus
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
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Pay range and Other Compensation & Benefits
$174,400.00 - $261,600.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
