Responsibilities
Digital design and development (RTL) working in close collaboration with Multi-site leads across US and India
Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC
Design and implement defined tasks independently.
Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed.
Analyze reports/waivers or run various tools : Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc.
Skills/Experience Sr Engineer / Staff Engineer
5 to 8 years of strong experience in digital front end design for ASICs
Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains and multiple power domains
Familiar with UPF and power domain crossing
Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI
Experience in low power design methodology and clock domain crossing designs
Experience in Spyglass Lint/CDC checks and waiver creation
Experience in formal verification with Cadence LEC
Understanding of full RTL to GDS flow to interact with DFT and PD teams
Expertise in Perl, TCL language
Expertise in post-Si debug is a plus
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Pay range and Other Compensation & Benefits
$129,600.00 - $179,600.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.
If you would like more information about this role, please contact Qualcomm Careers.
