Responsibilities includes but not limited to
Create highly scalable SoC architecture with expertise in the area of SoC control, boot, reset, timebase management, debug, micro-controllers, etc.
Comprehend product requirements to steer generation of proper architecture.
Perform trade-off analysis in the solution space to produce the most optimal architecture.
Collaborate with architects, technical leads, hardware and software engineers from various functional areas in deriving the architectural solution that can best integrate in the overall SoC.
Generate detail architectural specification and work closely with design team to implement the architecture.
Skills/Experience
Experienced in ARM and RISC-V AP architecture.
Excellent communication, documentation, and interpersonal skills with ability to convey proposals and interact effectively across a distributed multi-discipline organization
Strong foundation of silicon design principles and architectural trade-offs
Ability to span and connect levels of abstraction across system-design, high-level languages, OS, HW/SW interface, micro-architecture, and silicon implementation
Background in architecture (IP or SoC), and/or front-end design/verification (micro-architecture)
Demonstrated deep technical knowledge and achievements at the SoC, sub-system or large IP levels as micro-architect or architect
Ability to apply appropriate abstractions and quantitative analysis for problem definition and solutions
Experience in using, improving, and developing a variety of tools for analysis and modeling, such as functional and performance simulators, profilers, etc.
Programming ability for modeling and automation (OOP C++, Python preferred) with experience in software development best practices including reviews, unit-testing, version control, etc.
Ability and desire to develop and improve architecture methodologies for experiments and analysis
Preferred with experience in the SoC areas such as boot, timebase management and network, security architecture, reset architecture and debug architecture, system level control/management with components such as BMC, ECU, etc.
