An ideal candidate combines expertise in Clocking, DVFS, Power Management, PMIC, Firmware, Silicon Bring-up, and AI/HPC platform validation
Roles & Responsibilities
Own the E2E bare metal framework validation SoC clock and power architectures
Validation planning – understand design changes, visualize standalone and system level test requirements and scenarios
Test plan development – clearly document test strategy and dependencies
Conduct validation strategy and test plan review with all stakeholders – architects, designers, verification engineers, software engineers
Develop scalable device drivers, standalone and system tests using C
Debug complex issues both on pre-Si and post-Si platforms, provide debug direction
Review validation platform schematics to ensure post-Si debug support – might have to work with platform design team
Automate validation process – development, execution, inference using python, perl, shell
Use lab instruments – multimeter, oscilloscopes , logic analyzer
Efficiently collaborate with teams in different time zones – both internal and external
Minimum Requirements
Bachelor’s degree in engineering (electronics, computer engineering etc.)
5+ years of relevant experience in SoC validation and / or associated areas (SW development, embedded systems etc.)
Prior work experience in clock/ power validation
Proficient in C, Python
Experienced in using lab instruments – multimeter, oscilloscopes , logic analyzers
Exposure to debug tools (JTAG etc.). Knowledge of debug methodology of ARM based SoCs
Very good at problem solving - analytical and debugging skills
Preferred Qualifications
Prior exposure to below SW skills would add an edge above other applicants:
Experience with Cross-Compilers, Linkers and makefiles
Understanding of coherency and concurrency in modern SoC architecture
Knowledge of PMIC/ prior experience in validating rail power (power measurement tools/ setups)
Knowledge of pre-Silicon validation and debug on FPGA based emulation platforms is a plus
Knowledge of RTL and HDLs (Verilog/ System Verilog) would be an additional advantage
Should have prior work experience in a cross functional matrix work environment
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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