Work with microarchitecture, RTL, CAD, circuit, block-level physical design, and top-level physical design teams to understand, implement, and validate CPU clocking requirements.
Architect, implement, and optimize low-skew, low-power clock networks using approaches such as clock H-trees, clock mesh, clock spines clocking methodologies
Partner with CAD and physical design teams to develop and deploy clocking techniques that optimize skew, latency, clock power, timing margin, routability, and design convergence.
Use SPICE simulation and circuit-level analysis to validate clock circuits, clock paths, and electrical behaviour across process, voltage, and temperature conditions.
Analyse and debug clock-related timing, power, noise, variation, and physical implementation issues across multiple modes, corners, and operating conditions.
Provide feedback and guidance to block-level and top-level physical design engineers on required clocking fixes, optimization opportunities, and signoff risks.
Collaborate with PLL, timing, power, CAD, and implementation teams to align clock source assumptions, jitter budgets, clock uncertainty, and signoff methodology.
Develop, document, and improve clock construction, analysis, and validation flows for future CPU generations.
For Staff-level candidates, provide technical leadership, mentor engineers, influence cross-functional methodology, and drive resolution of critical clocking challenges.
Required Skills and Experience
We are looking for candidates with strong experience in CPU clocking, physical design, timing, and circuit-aware implementation.
The ideal candidate will have
Strong experience in the construction and analysis of low-skew and low-power clock generation and distribution networks.
Hands-on experience with clock distribution structures and methodologies such as Clock H-tree, Clock Mesh, Clock Spines
Strong understanding of CTS, clock balancing, insertion delay, skew optimization, useful skew, clock power reduction, and clock latency trade-offs.
Good understanding of device physics, RC delay, signal integrity, variation, and electrical effects that influence clock quality and timing robustness.
Proficiency in SPICE simulation and analysis for circuit design, clock-path validation, and electrical verification.
Strong understanding of static timing analysis and the interaction between clock architecture, timing closure, jitter, uncertainty, OCV/AOCV/POCV, setup/hold closure, and signoff quality.
Ability to debug complex clocking issues across implementation, timing, power, noise, variation, and circuit domains.
Experience working with industry-standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification.
Strong communication skills and the ability to work effectively with global, cross-functional engineering teams.
Minimum Qualifications
Candidates should typically have one of the following
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.
OR
Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.
OR
PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in CPU design, physical implementation, clock design, or circuit-aware methodology.
The role is intended for experienced candidates and is open for Staff Engineer level.
Preferred Qualifications
Experience in any of the following areas would be highly valuable
Experience defining or deploying clock methodology across multiple designs, projects, or technology generations.
Strong background in chip-level or top-level physical design, block integration, standard-cell optimization, and clock construction.
Experience working in advanced semiconductor process nodes, especially 7nm and below.
Proficiency with PLL specifications, clock source modelling, skew estimation, jitter budgeting, and jitter measurements. Experience with high-frequency CPU or high-performance compute clocking.
Experience with power-aware clocking, clock gating, resonant or mesh-based clocking strategies, and clock power optimization.
Familiarity with multi-corner multi-mode timing closure and variation-aware implementation methodologies.
Experience developing automation or analysis flows using TCL, Python, Perl, or similar scripting languages.
For Staff-level candidates, demonstrated ability to lead technical initiatives, influence cross-functional teams, define methodology, and mentor other engineers.
What We Value
We are especially interested in engineers who
Have deep clocking, timing, and physical design fundamentals.
Enjoy solving difficult clock distribution, skew, jitter, power, and signoff challenges.
Can balance circuit-level detail with top-level implementation and product-level constraints.
Are passionate about enabling high-frequency, power-efficient data center CPU designs.
Bring a structured, analytical, and data-driven approach to debug and methodology improvement.
Communicate clearly across microarchitecture, RTL, circuits, CAD, timing, and physical design teams.
Demonstrate ownership, technical curiosity, and a continuous-improvement mindset.
Benefits and Perks
At Qualcomm, you will be part of a collaborative engineering culture focused on innovation, technical excellence, and meaningful product impact.
We offer
Competitive compensation package, including base salary, performance-related bonus, and equity opportunities.
Employee Stock Purchase Plan and equity programs supporting employee share ownership and long-term participation in Qualcomm’s success.
Pension and retirement support, including a matching pension scheme.
Health and wellbeing benefits, including medical, life, income protection, and wellbeing resources.
Maternity, paternity, family, and extended leave support to help employees balance professional and personal commitments.
Education assistance and tuition support to enable continued learning and professional development.
Relocation and immigration support where applicable, particularly for strong candidates moving to join the Cambridge team.
Employee assistance and resilience programs supporting mental wellbeing, balance, and personal resilience.
Opportunities to connect through employee networks, community programs, volunteering, and social groups that support inclusion, collaboration, and community engagement.
Subsidised wellbeing and lifestyle benefits, which may include gym or fitness support, bicycle purchase schemes, and employee clubs.
A flexible, collaborative, and technically challenging work environment, with the opportunity to work alongside highly skilled engineers on advanced CPU technology.
Why Join the Nuvia Data Center CPU Team in Cambridge?
Cambridge is Qualcomm’s largest office in the UK, with approximately 400 team members across engineering, business strategy, and support functions. From an engineering perspective, the Cambridge site includes teams focused on RF and PMU analog design, digital design and verification, digital physical design, embedded software, packaging, and post-silicon validation. Target products include high-performance CPUs and GPUs, ultra-low-power IoT devices, and wearables such as smart glasses, smart watches, and earbuds.
The Nuvia Data Center CPU team is building advanced custom CPU technology for next-generation compute platforms. As a CPU Clock Physical Design Engineer, you will play a key role in shaping the clocking architecture and physical implementation methodology that enables high-frequency, power-efficient server-class CPU products.
This is an opportunity to work on technically demanding CPU clocking challenges, influence future-generation design methodology, and make a direct impact on world-class silicon products
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
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