Collaborate with DFT and physical design teams for successful integration and tapeout.
Minimum Qualifications
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
- OR
- Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
- OR
- PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Required Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
5+ years of experience in ASIC/SoC front-end design.
Strong knowledge of digital design fundamentals.
Hands-on expertise in
o RTL design using Verilog/SystemVerilog
Micro-architecture definition and documentation
Lint tools (SpyGlass, Questa Lint, or equivalent)
CDC/RDC tools (SpyGlass CDC, Questa CDC, or equivalent)
Good understanding of clocking architectures, reset strategies, and low-power design concepts.
Experience debugging RTL and simulation issues.
Preferred Qualifications
Experience with synthesis flows using Design Compiler, Genus, or equivalent tools.
Experience creating and reviewing timing constraints (SDC).
Understanding of timing analysis concepts including setup/hold, clock domain crossings, and timing closure.
Exposure to DFT methodologies and integration.
Knowledge of low-power design techniques (UPF/CPF).
Experience with complex SoC/IP development and integration.
Desired Skills
Strong analytical and debugging skills.
Excellent written and verbal communication.
Ability to work independently and drive block ownership.
Strong collaboration skills across architecture, verification, and physical design teams.
Nice to Have
Experience working on high-performance CPU, DSP, AI/ML, networking, multimedia, or connectivity IPs.
Scripting knowledge in Python, Perl, or TCL for automation and flow enhancement.
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