o Use simulation and formal verification methodologies to execute test plans, develop testbench components like checkers, assertions, stimulus generators.
o Work closely with system architects, design team, software teams and Soc team to validate system use cases.
o Work closely with emulation team to enable verification on emulators and FPGA platforms.
o Debug and triage failures in simulation, emulation and/or Silicon.
BE/BTech degree in CS/EE with 4+ years’ experience.
o Implementation of assembly and C language tests for verifying CPU architecture.
o Experience in C/C++, scripting languages, HDLS like Verilog/System Verilog
o Good Understanding of CPU architectures and CPU micro-architectures. Industry experience with CPU architecture (eg: x86, ARM, MIPS, RISCV, POWER) will be a plus
o Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.
Preferred Requirements
o Strong understanding of power management features in CPUs and CPU based Socs.
o In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture
o Experience with advanced verification techniques such as formal and assertions is a plus
o Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus
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