Track HC and NRE against plan as scope and schedules change. Work with Finance on forecasts and spend, and flag drift early with options to close the gap.
Own risk management: maintain the CHS risk and issue register, score risks, define mitigation and contingency plans, and drive them to closure.
Own change request management: assess the impact on CHS schedule, resources, and cost, and drive decisions with stakeholders.
Own tape-out checklist (TOCL) management: track checklist items and sign-offs with engineering leads, and drive them to closure ahead of each tape-out.
Drive chipset core meetings: own the agenda, capture decisions and action items, and follow up to closure.
Escalate schedule, resource, or technical risks to leadership on time, with a recommendation.
Set a regular status cadence for leadership covering schedule trends against baseline, top risks, and decisions needed. Prepare executive briefings for Director and VP audiences.
Use AI tools and automation to build dashboards, track program health, and reduce manual reporting (for example Microsoft 365 Copilot and agents, Power BI, Power Automate, JIRA).
Minimum Qualifications
- Bachelor's degree in Engineering, Computer Science, or related field.
- 2+ years of Program Management or related work experience.
Completed advanced degrees in a relevant field may be substituted for up to two years (Master’s = one year, Doctorate = two years) of work experience.
Preferred Qualifications
Bachelor's or Master's degree in Engineering (Electrical, Electronics, Computer, Mechanical, Materials, or a related engineering discipline).
2+ years of Program Management or related work experience.
Direct experience in semiconductor development or manufacturing. Candidates without semiconductor experience will not be considered.
Working knowledge of the SoC and silicon product lifecycle, from architecture and tape-out through bring-up, qualification, and customer sampling.
Understanding of IC package design and development, including substrate design, tape-out, and assembly.
Experience with headcount (HC) and NRE planning, tracking, and forecasting for engineering programs.
Hands-on experience with project management tools such as MS Project and JIRA, including building integrated schedules with cross-team dependencies.
Hands-on experience using AI tools (such as Microsoft 365 Copilot or AI agents) to automate reporting, analysis, and routine program work.
Strong communication and presentation skills, with the ability to explain technical trade-offs to engineering teams and leadership.
PMP certification or equivalent.
Experience in the HW SoC development cycle.
Package engineering, SI/PI, thermal, or test engineering experience before moving into program management.
2+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).
2+ years of experience working in a large matrixed organization.
2+ years of experience with program management tools such as dashboards (Splunk, ThoughtSpot, Tableau, Power BI/Power Automate, Agentic AI), Gantt charts, etc.
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Pay range and Other Compensation & Benefits
$132,800.00 - $199,200.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
