Responsibilities
Develop and execute validation plans and coverage, leveraging expertise in PMICs to enhance system-level validation strategies.
SoC–PMIC interface validation: Validate the SPMI (or similar, e.g., I2C/I3C) controller, PMIC arbiter and protocol behavior, including command sequences, arbitration across multiple masters, register access, interrupt handling and error/fault scenarios.
Sleep/wake and power sequencing: Define and execute scenarios covering power-on/power-off, reset, sleep entry/exit and wake-up sequences, including rail ramp/retention/collapse, clock (XO) handling, PMIC mode transitions and wake sources such as interrupts, RTC alarms and key presses.
Rail and regulator validation: Validate SoC-driven voltage scaling (DVFS/AVS), regulator mode switching (e.g., PWM/PFM, low-power/high-power), slew rates, settling times and voltage margins across supply rails.
Collaborate closely with cross-functional teams (SoC design, PMIC design/systems, power architecture, firmware and software) to validate power management subsystems and SoC Power infrastructure.
Measure and analyze power/performance characteristics of SoCs, with a focus on PMIC integration, rail-level current, sleep floor current and transition behavior.
Create random stress stimulus validation frameworks, incorporating PMIC scenarios (concurrent rail transitions, repeated sleep/wake cycles, load transients, interface traffic) to test system resilience and reliability.
Debug and root-cause silicon failures using lab tools, waveform captures and protocol traces; clearly document issues and drive them to closure with design and firmware teams.
Contribute to pre-silicon validation (emulation/FPGA platforms) to ensure PMIC-related scenarios are ready ahead of silicon arrival.
Job Qualifications
Bachelor's/Master's in Electrical/Electronic Engineering or Computer Engineering.
4-8 years of relevant industry experience in PMICs, defining and executing SOC level use cases and scenarios.
PMIC internals: Strong understanding of buck/SMPS regulators, LDOs, operating modes, power-on/power-off logic, PMIC GPIOs, ADCs, RTC, temperature alarms and protection mechanisms (OCP, OVP, UVLO).
Interface and protocol: Hands-on experience with SPMI or similar controllers and protocols (I2C/I3C), including PMIC arbitration, register access and interrupt flows.
