Create/Enhance low power methodologies covering entire design cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle and work on fixing any issues.
Provide feedback for low-power chip and system architecture.
Understand and perform block & chip-level power analysis.
Understand and create block-level power models.
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- OR
- PhD in Science, Engineering, or related field.
Minimum Qualification
3 years of experience doing low power digital ASIC design.
Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA.
Familiar with scripting languages like Python, Perl, TCL
Understanding of electrical engineering concepts, circuit analysis and logic design skills.
Preferred Qualifications
Previous experience in AVS (adaptive voltage scaling) desired.
Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high speed clocking desired.
Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc.
Good understanding of SoC architecture/micro-architecture.
Understanding of automotive functional safety standard ISO 26262 and analysis technique (FMEA/FMEDA) is a plus.
Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments.
Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap.
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