Experience in all aspects of timing closure for multi-clock domain designs.
Should be familiar with MCMM synthesis and optimization.
Should have good understanding of low-power design implementation using UPF.
Experience with scripting language such as Perl/ Python, TCL.
Experience with different power optimization flows or technique such as clock gating.
Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation
Should be able to handle ECOs and formal verification and maintain high quality matrix
Skill Set
Proficiency in Python/Tcl
Familiar with Synthesis tools (Fusion Compiler/Genus),
Fair knowledge in LEC, LP signoff tools
Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking
Familiarity with standard software engineering practices like Version
Control, Configuration Management, Regression is a plus
Should be sincere, dedicated and willing to take up new challenges
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