The ideal candidate possesses deep expertise in DDR/HBM technologies, memory controller architectures, silicon bring-up, and system-level debug.
Key Responsibilities
Memory Bring-Up & Validation
Own end-to-end HBM validation strategy from emulation through production silicon.
Develop comprehensive validation plans covering
o Memory initialization
o Training flows
o Power-state transitions
o Reliability testing
o Error recovery mechanisms
o Manufacturing diagnostics
o Reliability & RAS Validation
Drive Pre-silicon memory bring-up
Drive first-silicon memory bring-up and root-cause analysis of failures.
System-Level Validation
Validate interaction between
o HBM
o AI accelerators
o Compute fabrics
o Cache hierarchy
o NoC infrastructure
Develop stress scenarios representing real-world AI workloads.
Debug & Root Cause Analysis
Lead complex silicon debug efforts.
Analyze crashes, hangs, data corruption, training failures, and performance bottlenecks.
Collaborate with
o Memory architecture teams
o PHY teams
o Firmware teams
o Package and SI/PI teams
o AI software teams
Automation & Methodology
Develop scalable automation frameworks for memory validation.
Build telemetry, analytics, debug, and performance-monitoring tools.
Leverage AI-assisted validation and debug methodologies to improve productivity and coverage.
Required Qualifications
BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
8+ years of experience in memory validation, silicon validation, or platform bring-up.
Strong understanding of
DDR4/DDR5/LPDDR5/LPDDR6 architectures
HBM technologies
Memory controllers
PHY architectures
Cache and coherency systems
Experience with
Pre-silicon validation
FPGA platforms
Post-silicon bring-up
Strong debugging skills using
Logic analyzers
Protocol analyzers
Performance counters
Firmware traces
Programming experience in Python, C/C++.
Preferred Qualifications
Prior experience validating
HBM2, HBM3, HBM3E, Advanced stacked-memory technologies
Experience with AI accelerator, GPU, HPC, or server-class platforms.
Familiarity with: NoCs, Chiplets, Coherent interconnects
Knowledge of
Signal Integrity (SI)
Power Integrity (PI)
Thermal characterization
Package-level interactions
Experience defining validation methodologies for first-generation memory technologies.
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
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Pay range and Other Compensation & Benefits
$174,400.00 - $261,600.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
