Company
Qualcomm Semiconductor Limited
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
Key responsibilities
Drive PPAC assessment and technology pathfinding for System-Technology Co-Optimization (STCO) and heterogeneous integration.
Evaluate and develop 2.5D/3D chiplet integration solutions, including SoIC, CoWoS, WoW, hybrid bonding, interposer, and RDL technologies.
Perform custom DRAM and 3D SRAM integration evaluation and pathfinding for advanced product development.
Develop and support test-chip design, mask layout, design flows, and PDK enablement for advanced silicon and packaging technologies.
Perform layout and design analysis for advanced technology benchmarking, DFM, and product issue debugging.
Develop and assess advanced system PDN solutions and system-level KPIs.
Serve as a technical interface with foundries, supporting technology evaluation, design enablement, and STCO activities.
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Desired Skillset / Experience
Strong experience in 2.5D/3D heterogeneous integration, STCO, and technology pathfinding.
Hands-on experience with physical design and custom layout in advanced silicon technologies, preferably sub-10nm.
Experience with heterogeneous integration technologies such as hybrid bonding, wafer bonding, TSV, micro-bump/u-bump, RDL, and backside metallization.
Experience with TSMC SoIC and/or CoWoS product or technology development is highly desirable.
Hands-on experience with PDK development and verification flows, including DRC, LVS, PEX, and DFM.
Proficiency with Calibre, Cadence, SVRF, TCL, and related scripting/design automation.
Experience in test-chip design, mask layout, tapeout, and silicon execution.
Experience with technology benchmarking and PPAC assessment for advanced technology nodes.
Knowledge of system PDN, Power Integrity (PI), and Signal Integrity (SI) is a plus.
Experience with process integration and/or unit process development is highly desirable.
Experience with 3D cache/SRAM architecture and partitioning is a plus.
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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