Work with tool vendors and push the methodology to improve the area/performance of the synthesized FPGA RTL.
Work on third-party IP integration and system-level debugging.
System level RTL simulation & design verification.
Support chip bring up and post silicon debug.
Debug functional and timing models.
Preferred Qualifications
Bachelors degree in Science, Engineering, or closely related field
1+ years of hands on experience in emulation/simulation acceleration/FPGA.
1+ years in Design validation/Post-Silicon debug.
1+ years of hands on experience in creating high performance & area efficient emulation environments from RTL.
1+ years of hands on emulator platforms, platform bringup, digital design, verification, debugging, and waveform viewers
1+ Hardware emulators, such as Palladium, ZeBu, Veloce, or FPGA systems based on Xilinx or Altera FPGAs
1+ Emulation methodologies, including in-circuit emulation, hybrid systems, or simulation acceleration
Desirable Skills
MS degree in Electrical Engineering or equivalent; 1 year of practical experience
Design Verification knowledge – UVM/System Verilog preferred
Knowledge of GPU/CPU/DDR/Bus preferred
Verilog and System Verilog experience.
Debugging system-level software, Debug RTL
Programming skills in C and C++
Scripting in Python, Tcl, or Perl
Knowledge of Vendor Emulation tools/Xilinx tools/Synthesis tools
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