Preferred Qualifications
15+ years industry experience in the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power and multi voltage domain designs. A strong fundamental knowledge of DFT is required
Understanding of core-based test methodology and scan isolation.
Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing.
Experience with industry EDA ATPG and insertion tools.
Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis.
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Pay range and Other Compensation & Benefits
