Create and execute constrained-random, directed, error-injection, and corner-case tests.
Write and maintain SystemVerilog Assertions for protocol, interface, timing, and functional verification.
Verify memory-controller, PHY-interface, and memory-subsystem functionality across multiple operating modes.
Analyze simulation failures using waveform viewers, simulation logs, transaction databases, and other debug tools.
Perform root-cause analysis of verification failures and collaborate with RTL, architecture, modeling, and integration teams to resolve issues.
Review RTL, microarchitecture specifications, interface definitions, and design changes for functional correctness, completeness, and verifiability.
Support regression execution, failure triage, failure classification, and verification status reporting.
Drive functional, code, assertion, and coverage closure.
Collaborate with cross-functional teams, including architecture, design, physical design, firmware, modeling, and system validation teams.
Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
3–10 years of experience in ASIC, SoC, IP, or subsystem design verification.
Strong hands-on experience with
Verilog
SystemVerilog
UVM
SystemVerilog Assertions
Experience developing and debugging reusable UVM-based verification environments.
Proficiency in developing UVM components such as sequences, drivers, monitors, scoreboards, agents, and functional coverage models.
Experience with constrained-random verification and coverage-driven verification methodologies.
Experience writing assertions for protocol compliance, temporal behavior, interface checking, and functional correctness.
Strong understanding of digital design and verification fundamentals, including clocking, reset behavior, synchronous and asynchronous logic, and multi-clock-domain designs.
Experience with simulation-based verification, waveform analysis, regression execution, and failure debug.
Strong analytical, problem-solving, communication, and collaboration skills.
Preferred Qualifications
Experience verifying LPDDR, DDR, DDR PHY, HBM, custom memory interfaces.
Familiarity with JEDEC memory specifications and memory-protocol requirements.
Understanding of memory-controller, memory-subsystem, and PHY architecture.
Familiarity with integrating and configuring industry-standard verification IP.
Experience working with commercial or internally developed memory models.
Experience with power-aware simulation using UPF.
Knowledge of standard interfaces such as AXI, APB, AHB, DFI, or similar protocols.
Experience with formal verification or assertion-based verification methodologies.
Experience verifying high-performance, low-power, or multi-clock-domain designs.
Experience with performance verification, including bandwidth, latency, throughput, efficiency, QoS, and stress testing of memory subsystems.
Familiarity with hardware/software co-verification or system-level validation.
Experience with memory training, initialization, refresh, power-management, frequency-switching, calibration, or error-handling scenarios.
Minimum Qualifications
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- OR
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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Pay range and Other Compensation & Benefits
$159,600.00 - $239,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
