Create directed, constrained-random, stress, performance, power, and system-level test scenarios to validate architecture and real-use-case behavior.
Develop assertions, functional coverage models, checkers, scoreboards, and signoff metrics for verification closure.
Debug RTL, testbench and silicon bring-up issues using logs, waveforms, traces, and hardware debug data.
Drive coverage closure, regression health, bug tracking, and verification signoff using functional, code, assertion, and scenario coverage metrics.
Minimum Qualifications
Bachelor's or Master’s degree in Electical Engineering, with GPA of 85 and above.
Strong analytical and problem-solving abilities.
Demonstrated aptitude for learning new technologies quickly.
Excellent communication and collaboration skills.
Ability to work independently and as part of a team.
Passion for innovation and continuous improvement.
Preferred Qualifications
Verilog/System Verilog knowledge
Knowledge and experience in verification
Strong programming background
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field.
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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