Experience in developing constraints for multi-clock domains hierarchical/flat timing analysis
Good working knowledge in multi-power domain synthesis and structural power checks using CLP.
Hands-on experience in Formal verification along with strong debugging skills for resolving issues/aborts.
Good working knowledge in Pre-layout STA and analyzing timing reports and generating timing ECOs
Good knowledge on analyzing trade-offs and recipes for timing/area/power/congestion.
Exposure in TCL scripting for usage in Synthesis/STA
Knowledge on Hierarchical STA with Hyperscale is a plus
Good team player. Need to interact with the stakeholders proactively
Ability to debug and solve issues independently
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Pay range and Other Compensation & Benefits
$147,900.00 - $221,900.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
