Necessary skills/experience
3+ years of experience in RTL design verification using SystemVerilog/UVM and industry-standard simulation tools (Mandatory)
Experience in power aware simulation is a big plus
Experience on camera verification is a big plus
Expertise in Coverage closure , RTL debug skills
Expertize in SV – UVM, Assertions based verification, DPI
Familiarity in Firmware/emulation (ex: Veloce) based verification , GLS
Familiarity with bus protocols like AHB, AXI, ARM based system architecture
Experience with Perl, Python, or similar scripting language
Excellent problem solving skills & Verification aptitude
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