Design and implement AI-driven agentic workflows to enhance verification productivity.
Skills Set
Experience with design verification defining test plans, developing verification infrastructure using OOP and execution of defined test plans to meet required Metrics of Closure
Expertise with Hardware verification languages (HVL) such as System Verilog testbench (OVM/UVM)
Development of Directed and Constrained Random stimulus
Strong Digital Design concepts and debugging skills with expertise in traversing Verilog/System-Verilog RTL
Minimum Qualifications
- Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
- OR
- Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
- OR
- PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.
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Pay range and Other Compensation & Benefits
$155,400.00 - $233,200.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
