Work closely with FW, architecture, VLSI design and verification teams for blocks/system ASIC implementation and validation
Perform post silicon activities, including chip bring-up, testing, analysis, and optimization of the ASIC performance
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Communication Engineering or related field and 2+ years of Algo/Systems Engineering or related work experience.
OR
Master's degree in Electrical Engineering, Communication Engineering, or related field and 1+ year of Algo/Systems Engineering or related work experience.
OR
PhD in Electrical Engineering, Communication Engineering, or related field.
Preferred Qualifications
Master's Degree in Electrical Engineering, Communication Engineering or related field.
4+ years of Algo/Systems Engineering or related work experience.
Experience in high speed communication, i.e. SerDes, PCIE. Experience with optics - advantage.
Expertise in error correction codes - must.
1+ year of work experience in a role requiring interaction with senior leadership (e.g., Sr. Staff level and above).
References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
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