Identify, recommend, and implement new systems, tools, processes, and technologies to improve design, reuse organizational processes and decision-making
Support post-silicon validation activities for your designs.
BS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
The ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status
Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)
Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
Experience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers
Good understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages
Understanding of digital architecture trade-offs for power, performance, and area
Must have good written and verbal cross-functional communication skills
BE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience
#LI-RT1
Responsibilities for Internal Candidates
Qualifications
BS in Electrical Engineering or related + 10 years of experience, or MS + 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
The ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status
Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)
Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
Experience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers
Good understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages
Understanding of digital architecture trade-offs for power, performance, and area
Must have good written and verbal cross-functional communication skills
BE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience
#LI-RT1
Qualifications for Internal Candidates
Qualifications
BS in Electrical Engineering or related &; 10 years of experience, or MS ; 8 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments
The ideal candidate should have thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status
Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF and system Verilog (assertion)
Solid understanding of Verilog, TCL and Perl/Python/XML programming languages
Experience in developing ASIC/Mixed signal ICs for various Power Converters such as multiphase converter, DC-DC PMIC/POL, AC-DC converters, LED drivers
Good understanding of topologies and architectures for Constant-on-time, Peak, and Valley Current/Voltage Mode control mechanism, Hysteretic, Multi-Phase Controllers, and Smart Power Stages
Understanding of digital architecture trade-offs for power, performance, and area
Must have good written and verbal cross-functional communication skills
BE/BTech in Electrical Engineering or related + 10 years of experience, or MTech + 8 years of experience
#LI-RT1
Same Posting Description for Internal and External Candidates