onsemi
From onsemi's careers page
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Job Summary We are seeking a motivated Analog Layout Engineer with strong hands-on experience in custom analog and mixed-signal layout development.
Job Summary
We are seeking a motivated Analog Layout Engineer with strong hands-on experience in custom analog and mixed-signal layout development. The candidate should have a solid understanding of analog layout fundamentals, matching techniques, process understanding, and verification closure. Experience in higher-node technologies and DNW-based layouts is preferred.
Develop high-quality custom analog and mixed-signal layouts from schematics.
Implement device matching, common-centroid structures, shielding, guard rings, symmetry, and parasitic-aware layout techniques.
Perform layout verification and achieve clean DRC, LVS, and ERC sign-off.
Debug DRC/LVS issues independently and drive closure efficiently.
Understand and interpret process cross-sections, layer interactions, and device structures.
Work closely with circuit designers to ensure proper implementation of design intent.
Participate in layout reviews and incorporate feedback for quality improvements.
Support extraction and post-layout verification activities.
#LI-RG1
Job Summary
We are seeking a motivated Analog Layout Engineer with strong hands-on experience in custom analog and mixed-signal layout development. The candidate should have a solid understanding of analog layout fundamentals, matching techniques, process understanding, and verification closure. Experience in higher-node technologies and DNW-based layouts is preferred.
Develop high-quality custom analog and mixed-signal layouts from schematics.
Implement device matching, common-centroid structures, shielding, guard rings, symmetry, and parasitic-aware layout techniques.
Perform layout verification and achieve clean DRC, LVS, and ERC sign-off.
Debug DRC/LVS issues independently and drive closure efficiently.
Understand and interpret process cross-sections, layer interactions, and device structures.
Work closely with circuit designers to ensure proper implementation of design intent.
Participate in layout reviews and incorporate feedback for quality improvements.
Support extraction and post-layout verification activities.
#LI-RG1
Required Skills
B.E (Electronics, E&TC or relevant field)
2-3 years of hands-on analog/custom layout experience.
Device matching techniques
Common centroid layouts
Interdigitization
Guard rings and shielding
Latch-up prevention concepts
Analog routing methodologies
Good understanding of semiconductor process technology and device cross-sections.
Experience with Deep N-Well (DNW) processes is preferred.
Strong debugging skills in DRC/LVS verification.
Good, logical reasoning and analytical problem-solving skills.
Familiarity with Cadence Virtuoso and industry-standard verification flows.
Good communication and teamwork skills.
#LI-RG1
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