Advanced development: Exploring the potential of future process nodes and developing techniques to realize optimal power, performance, and area characteristics.
Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners to help them achieve their overall performance and cost goals, guide the silicon test and characterization efforts, and working with productization teams to prepare new silicon for the demanding requirements of real-world applications.
What we need to see
BSEE minimum (or equivalent experience), MSEE or PhD
2+ years of professional experience in SRAM design
Familiarity with Cadence Virtuoso schematic and layout capture tools
Willingness and ability to use AI effectively in day-to-day tasks
Ways to stand out from the crowd
Self-motivation, attention to detail, and good written, verbal, and presentation skills are essential to success in this role
We rely heavily on AI coding and analysis tools such as Codex and Claude Code. The more developed your skills in this area, the better
Silicon testing and debugging experience
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 116,000 USD – 189,750 USD.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
