Direct custom layout and verification of complex memory cells, setting standards and methodologies for compiler-driven design flows.
Be responsible for and optimize all physical verification activities, including DRC, LVS, density analysis, and comprehensive tape-out checks.
Drive the identification and resolution of complex physical design issues in compiler-generated layouts, mentoring junior engineers in established methodologies.
Provide guidance on IR drop and EM mitigation strategies, establishing design methodologies for robust memory layouts.
Possess deep expertise in ultra-deep sub-micron layout challenges, regularly innovating and implementing advanced solutions.
Development of memory compilers, leading solving efforts and driving optimization for performance, area, and manufacturability.
Cultivate effective teamwork across multi-functional teams, influencing project direction and ensuring alignment with organizational objectives.
Excel in resource management, representing the team in technical discussions with customers
What we need to see
B.E/B Tech. / M Tech in Electronics or equivalent experience with 6+ Years of proven experience in Memory layout in advanced CMOS process.
Detailed knowledge of industry standard EDA tools for Cadence.
Experience with layout of high-performance memories of various types.
Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)
Experience with floor planning, block level routing and macro level assembly.
Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.
We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status
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