Lead the strategy for ATE platform selection, vendor engagement, capacity readiness, and capital planning needed to support product ramps.
Use data and analytics to improve silicon correlation, test limits, binning strategies, excursion response, and long-term product quality.
Build a high-performance leadership culture through strong hiring, interpersonal development, succession planning, and multi-functional influence.
What we need to see
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
18+ years of relevant semiconductor experience, including 8 + years of management experience. Leading managers and distributed engineering organizations.
Deep expertise in ATE development for high-volume silicon, SoC, ASIC, or GPU-class products.
Shown success leading organizations through NPI, silicon bring-up, characterization, production ramp, yield improvement, and quality execution.
Strong understanding of ATE platforms, test hardware design, test program development, instrumentation, silicon correlation, statistical analysis, and production test methodologies.
Consistent track record to partner across design, DFT, product engineering, failure analysis, reliability, manufacturing, and supplier or OSAT ecosystems.
Experience owning roadmaps, budgets, staffing plans, and operational priorities for large-scale engineering organizations.
Strong executive communication skills with the ability to influence senior collaborators and drive alignment across technical and business teams.
Ways to stand out from the crowd
Experience with GPU, AI, networking, or other high-performance compute products.
Track record of reducing test cost while improving outgoing quality and production scalability.
Strong background in test automation, data infrastructure, and improvement guided by data insights.
Experience building and scaling global test-development organizations across multiple sites and external partners.
Familiarity with system-level test, product binning, performance and power optimization, or silicon operations workflows.
With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. This role presents an opportunity to have a wide impact at NVIDIA by improving the factory planning function. Are you creative, hard-working, dedicated, and determined? Do you love a challenge? If so, we want to hear from you!
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary range for this position is 320,000 USD – 483,000 USD.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 3, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
