Continuously improve workflows and designs by introducing more automation, resilience, and standardization.
What we need to see
BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 2+ years’ experience.
Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes.
Expertise in analysis and fixing of timing paths through ECOs.
Expertise in developing timing constraints.
In-depth knowledge of industry standard timing convergence tools.
Ways to stand out from the crowd
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, iJTAG, etc.
Background in domain specific STA and timing convergence, such as Serdes, Processor, IO, SMVA, etc.
Experience in methodology and/or workflow development.
NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 6, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.