Build the test infrastructure, characterization methodologies, and bring-up playbooks that shift post-silicon coverage left and raise velocity across programs.
Lead root-cause analysis on the hardest HW/SW interaction issues — with the measurement field, instrumentation judgment, and hypothesis rigor to close them under schedule pressure.
Identify where current processes break and redesign them: bring-up sequencing, debug forums, regression frameworks, and the lab metrics that tell us whether we are actually improving.
What we need to see
BS or MS in Electrical or Computer Engineering (or equivalent experience), plus 5+ years in silicon bring-up, validation, debug, or productization.
Deep fundamentals across digital development, microarchitecture, timing, clocking, power, noise, and control systems — and the ability to reason across the HW/SW boundary under real lab constraints.
Hands-on lab proficiency: oscilloscopes, logic analyzers, power analyzers, and the instinct to know which instrument answers which question during a bring-up.
Strong programming and scripting proficiency: Python, C/C++; experience building lab automation or test infrastructure that other specialists adopt and depend on — not just personal scripts.
Proficiency in the use of AI tools to accelerate silicon validation work — automated analysis of bring-up logs, regression data, or lab instrumentation output; anomaly detection on silicon measurement datasets; or LLM-assisted debug triage. We want to understand what you built, how you validated its trustworthiness, and where you decided the measurement had to stay manual.
Ways to stand out from the crowd
Hardware proof of crafting: debug infrastructure you built in the lab, characterization methodologies adopted across programs, build DFT feature specs or in-system test suites you developed, or margin test flows that caught issues before production.
Proficiency in bring-up experience with GPU/SoC architecture
Experience crafting or scaling in-system test and DFT features for production silicon, with familiarity with fault models, DPPM, and RAS.
Build concrete examples of redesigning how a team debugs in the lab — faster triage, smarter hypothesis trees, automated measurement reporting — and the resulting increase in bring-up velocity or quality.
Our team is at the forefront of innovation in silicon co-design, contributing to the development of groundbreaking technologies. We offer a dynamic work environment where your contributions will directly impact the company's success. Join us to advance your career in a role where you can truly make a difference. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers.
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
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Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until October 17, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
