What you will be doing
Own validation: a module, board section or small product, partnering with the Lead Validation Engineer from first power-on to mass production. Support test plan development and run in one or more areas such as power, high-speed IO, low-speed IO (I2C, SPI, UART, SMBus, GPIO), clocks/resets, BMC, sensors, telemetry and firmware.
Debug and root-cause: board, firmware and system issues from bring-up through production, using measurements and first-principles analysis.
Power validation: sequencing, load, transient and protection testing.
High-speed interfaces: PCIe, Ethernet and USB, using high-bandwidth scopes, TDR and protocol analyzers.
System stress testing: thermal, power, IO, memory and voltage/frequency corners to expose marginal failures, with clear reports on status, issues and risks.
Design review: schematics, layouts, BOMs and datasheets and giving timely feedback that improves the product.
NPI and production support: builds and debug at manufacturing sites, locally and overseas to help products ship on time.
Cross-functional and software work: partner with mechanical, design, industrial design, thermal, shock and vibration, EMI/EMC, software teams, plus JDM partners, vendors and teams in Asia and Europe, following issues through closure. Validate hardware with SBIOS, VBIOS, drivers, Windows, Linux, automotive OS and Android, and build test scripts and automation. Communicate status and risks and mentor interns and newer engineers.
What we need to see
BS or MS in EE/CE or equivalent experience, plus 2+ years of hands-on board or system hardware validation, bring-up or debug (internships and co-ops count).
EE fundamentals: very strong circuit analysis, digital design, transmission lines and power supplies, shown through projects and work.
Core validation: Strong hands-on experience in one or more areas such as power validation (regulators, sequencing, PDN, telemetry), high-speed IO validation (PCIe, Ethernet, USB, display or DDR), Low-speed IO (I2C, SPI, UART, SMBus, GPIO), system functional and stress testing.
Lab skills: hands-on with oscilloscopes, power supplies, electronic loads, DMMs, TDR and logic/protocol analyzers.
Design skills: working knowledge of schematics, PCB layout and BOM.
Debug skills: root-cause failures across board, firmware and software using measurements and first-principles reasoning.
Software skills: scripting or programming (Python or C/C++), comfortable in Linux and Windows. Android or automotive OS exposure is a plus.
Soft skills and passion: quick learner and clear communicator across teams, JDM partners, vendors and time zones. Personal hardware projects and a genuine drive to build products.
Logistics: on site in the Santa Clara lab five days a week and willing to travel to manufacturing sites near Santa Clara (typically up to 5%) to support NPI builds and un-gate factory.
Ways to stand out from the crowd
Breadth and platforms: hands-on expertise in more than one area (power, high-speed IO, low-speed IO or system stress testing), with bring-up or validation experience on GPU, server, automotive or embedded platforms.
Deeper power validation: multi-phase VR design validation or PDN characterization. High-speed IO electrical validation: eye diagram, compliance test, BERT, PCIe link training or DDR.
Automation and firmware: creating or automating system stress workloads, functional test suites or lab infrastructure, plus BMC/manageability or firmware debug.
Manufacturing and projects: factory build or NPI support, and hobby builds you designed, built and debugged (racing, drones, robotics), or tutoring or teaching assistant experience in circuits.
Able and willing to travel internationally (primarily to Asia mfg sites such as Taiwan, China mainland etc.), up to 8% during NPI peak, to support builds.
Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
- Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are:
- 108,000 USD – 184,000 USD for Level 2; and 136,000 USD – 212,750 USD for Level 3.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 17, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.