Architect RDMA-capable hardware and define transport layer optimizations for GPU-based large scale AI workload deployments.
Explore and build novel high-density multi-chiplet, multi-package, multi-node rack-scale AI systems consisting of hundreds/thousands of copper and optically interconnected GPUs.
Use and modify system models, perform simulations, and bottleneck analyses to guide design trade-offs.
Work with GPU ASIC, compiler, library, and software teams to enable efficient hardware-software co-design across compute, memory, and communication layers.
What we need to see
BS/MS/PhD in Electrical Engineering, Computer Engineering, or equivalent area.
2+ years or more of relevant experience in system design and/or ASIC/SoC architecture for GPU, CPU, XPU, or networking products.
Deep understanding of communication interconnect protocols such as Ethernet, InfiniBand, NVLink, CXL and PCIe.
Proven ability to architect multi-GPU/multi-CPU topologies, with awareness of bandwidth scaling, NUMA, memory models, coherency, and resilience.
Strong analytical and system modeling skills for performance, power, resilience.
Excellent cross-functional collaboration and skills.
Ways to stand out from the crowd
Experience with NICs, DPUs, RDMA/RoCE or InfiniBand transport offload architectures.
Expertise in chiplet interconnect architectures or multi-node fabrics and protocols for high-performance distributed computing.
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