Designing and running rigorous A/B and multi‑variant experiments to compare flows, engines, and tool settings. Developing Python‑based analytics and ML/GenAI techniques to mine large QoR datasets, recommend flow settings, and automate analysis.
Performing deep root‑cause analysis on QoR issues across engines, tools, and flows, and driving methodologies to resolve the ‘long tail’ of timing closure and performance limiters.
Partnering with architecture, RTL, DFT, synthesis, physical design, power, signoff, and CAD/methodology teams as a key technical leader and bridge.
Driving aggressive PPA and schedule targets and the adoption of new tools and flows across the company.
What we need to see
BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
8+ years physical design experience, with deep expertise in industry standard tools like ICC2/Innovus, PrimeTime/Tempus, etc.
Extensive hands‑on P&R experience taking complex blocks or chips to tape‑out with aggressive PPA targets.
Proven skills in Python, Perl, and TCL flow development.
Strong problem‑solving skills and self‑motivation, demonstrated by simplifying complex, cluttered environments and modernizing legacy tools and processes.
Excellent communication and collaboration skills, with a track record of driving consensus and solving complex issues across distributed design, CAD, and R&D teams.
Ways to stand out from the crowd
Experience collaborating with EDA or internal R&D teams on core engine development, co‑defining features, developing benchmarks and leading validation and deployment.
Expertise in designing and automating A/B tests and large‑scale regressions, and analyzing large QoR datasets to understand trends and drive root‑cause analysis.
Background in advanced‑node and large‑scale designs with exposure to advanced‑node challenges (DFM, variability, EM/IR, power integrity).
Hands‑on experience applying AI/ML or GenAI to physical design, QoR analysis, or flow development will be a strong plus.
If working hands‑on from early architecture and RTL through silicon, and serving as the connector between core developers, methodology teams, and users, excites you, we want to hear from you.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until May 23, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
