Building Python pipelines and analyses that turn prototype, DOE, simulation, and characterization data (power, noise, Vmin/Fmax, binning yield) into traces, summaries, and inputs for firmware tuning, product specs, and manufacturing limits — with checks for schema, units, corners, and SKU mapping.
Partnering with architecture, design, validation, and firmware to add debug hooks, iterate the prototype, and document what the experiment proved versus what still needs silicon char
Using secure, traceable, validated AI-assisted workflows for experiment planning, analysis, and documentation, with human oversight on any conclusion that could affect limits, bins, or specs.
What we need to see
MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Background in a related silicon, validation, characterization, productization (SoC, GPU, CPU, or similar).
Working knowledge of silicon circuit/clock/power/noise concepts — for example DVFS, Vmin/Fmax, shmoo, PDN/noise, Driver, or margins — and comfort with learning DOE and prototype bring-up in a co-design setting.
Hands-on experience with at least one of: lab or post-silicon bring-up, experiment or characterization campaigns or manufacturing test/limits that consume chip data.
Proficiency in Python (or similar) for data analysis, automation, and validation; comfort with Git and structured test/regression. SQL or lightweight dashboards are a plus.
Ability to turn an ambiguous silicon question into a measurable experiment, communicate clearly across teams, and write notes others can execute from.
Strong AI-enabled skills and thinking — use AI to accelerate analysis, exploration, and documentation while maintaining rigor, originality, and judgment that do not come from AI.
Ways to stand out from the crowd
You have run a test-chip, prototype vehicle, or characterization DOE and can explain what you would change in the next matrix.
Direct experience on GPU/SoC/CPU circuits, power, performance, PDN/noise, or sim-to-silicon correlation.
You have shipped an internal tool, dashboard, or data pipeline (Python, databases, web apps) that other people actually use.
Hands-on LLMs in an engineering workflow — agents, RAG, or evaluation — including a time you had to debug a incorrect or unsafe answer.
Exposure to firmware/BIOS parameters, eFuse/limits, or ATE/SLT screening, and how they connect to product SKUs.
