What you'll be doing
Chip integration and netlist generation
Synthesis
RTL/netlist quality check
Formal Verification
Constraints creation and validation, timing budget.
Work with ASIC team to analyze/resolve special timing issues.
Cross-Team collaboration to implement chip partitioning and floorplan
Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level
Achieve special mode timing closure, such as io, test, clock, async etc.
Function eco creation
Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)
Flow automation development for above areas
Methodology in any of above areas.
What we need to see
MS in EE or Microelectronics
Project experience in IC design implementation
Courses taken in circuit design, digital design
Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpful
Proficient user of Python or TCL is helpful
Proficient in English reading and writing
With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.