Amplifiers
Filters
Switched capacitor circuits
Oscillators
Data converters
Power management circuits
Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
Physical verification of custom IC mask layouts (LVS, DRC, ERC)
Required Qualifications
Bachelor of Science in Computer Engineering or related field
2+ years of experience in analog and mixed-signal IC layout design
1+ year experience with FinFET technologies
Ability to identify the best approach to solving problems
Preferred Qualifications
Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
Understanding on failure-prone circuit and layout structures
Experience with analog DFM standards
Experience with layout P-cell design and implementation
Experience with layout automation
Expected Compensation
The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.
Base Salary Range
$83,000—$200,000 USD
What We Offer
Full-time employees are eligible for the following benefits listed below.
An opportunity to change the world and work with some of the smartest and most talented experts from different fields
Growth potential; we rapidly advance team members who have an outsized impact
Excellent medical, dental, and vision insurance through a PPO plan
Paid holidays
Commuter benefits
Meals provided
Equity (RSUs) *Temporary Employees & Interns excluded
401(k) plan *Interns initially excluded until they work 1,000 hours
Parental leave *Temporary Employees & Interns excluded
Flexible time off *Temporary Employees & Interns excluded